RASHMITHA RANI B.N.; K.B. RAMESH. The Design and Micro-Architectural Performance Optimization of Parallel Adder Circuit. Recent Trends in Semiconductor and Sensor Technology, [S. l.], p. 9–17, 2024. Disponível em: https://www.matjournals.net/engineering/index.php/RTSST/article/view/522. Acesso em: 5 aug. 2026.