Design of a High-Performance Approximate Radix-4 Booth Multiplier with Optimized Compressor and Encoder for Energy-Efficient Computing - M. Durga Sravanthi; B. Sravya; B. Raghu Vardhan; R. V. Suresh Chandra; T. Subhashini (Journal of Microprocessor and Microcontroller Research, 2025)
This paper presents an optimized design of an Approximate Radix-4 Booth Multiplier (ARB4M) that enhances power efficiency, area utilization, and computational delay. The demand for energy-efficient arithmetic units has significantly increased due to the rising adoption of digital signal processing, machine learning accelerators, and other high-performance computing applications. Traditional booth multipliers require extensive hardware resources, making them unsuitable for resource-constrained environments. The proposed ARB4M employs an approximate computing approach that reduces the number of partial products and integrates an optimized compressor design to achieve significant power savings. Our implementation achieves a dynamic power consumption of 0.079 W, a critical path delay of 10ns, and area utilization of 740 LUTs, 640 FFs, and 200 IOBs. Previous studies have shown that approximate multipliers can achieve up to 40% power savings in error-resilient applications. By leveraging approximate radix-4 encoding, our design improves the power-delay product (PDP) compared to conventional multipliers. The energy per operation is estimated at 192pJ, making it a viable solution for error-tolerant applications such as image processing, low-power embedded systems, and neuromorphic computing. The co-optimization of approximate partial product generation (PPG) and approximate partial product accumulation (PPA) ensures an efficient balance between performance and accuracy, aligning with recent trends in approximate arithmetic circuit design. Experimental results indicate that the ARB4M achieves a 28% reduction in power consumption while maintaining computational accuracy suitable for DSP and artificial intelligence workloads. Future work includes adapting the architecture for ASIC implementations and exploring dynamic approximation techniques for further optimization. This research demonstrates that approximate computing principles can effectively optimize the power and performance in arithmetic circuits, making them suitable for energy-efficient hardware applications.