Design, Verification and Optimization of AMBA AHB Lite protocol
Keywords:
Advanced Microcontroller Bus Architecture (AMBA), Advanced High-Performance Bus (AHB), HRESP signal, HWDATA signal, Register Transfer Level (RTL), Transaction-level Modeling (TCL), Universal Verification Methodology (UVM)Abstract
This paper focuses on designing and optimizing a 32-bit dual port AHPB-Lite Protocol implemented module, modeling its components in Verilog HDL, and performance verification in System Verilog. The implementation methodologies are mainly based on the most popular ARM-based AMBA (Advanced Microcontroller Bus Architecture) AHPB, an on-chip bus interconnection-based protocol.
This project's enslaver, slave, decoder, and multiplexer modules have been designed separately and interconnected accordingly. Before the integration, each module was verified independently, and after the integration, all designed modules' inter-transactions were verified successfully using System Verilog.
AHPB-Lite is a synthesizable design, and all the modules are designed using mealy FSM technology as all transactions are based on input as well as the current state of the module. After all the successful transactions, now in the optimization stage, the power consumption parameter has been considered for the module and reduced the total power by, on average, 12.35% of the dynamic power using clock-gating technology over all the modules and at the interconnectivity.
