VEJENDLA, N.; DR.R., . R. R.; NARAYANAM, B. Novel Time-Domain Interleaved Multiplier Sharing Architecture for Ultra-High Throughput FFT Processors. Journal of VLSI Design and Signal Processing, [S. l.], v. 12, n. 1, p. 28–38, 2026. DOI: 10.46610/JOVDSP.2026.v12i01.003. Disponível em: https://www.matjournals.net/engineering/index.php/JOVDSP/article/view/3026. Acesso em: 3 aug. 2026.