Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED en-US Mon, 15 Jun 2026 08:31:50 +0000 OJS 3.3.0.8 http://blogs.law.harvard.edu/tech/rss 60 Constant Current Boost Converter for Auxiliary Battery Charging in Electric Vehicles https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3803 <p><em>As the world is shifting to EV transportation, the requirement for charging methods that are fast, efficient, and do not wear out batteries too quickly is also rising. Different approaches exist, and each has its own set of trade-offs. Some prioritize speed, others focus on battery health, and a few try to balance both. The proposed system dives into the design and simulation of a lithium-ion battery charging system for electric vehicles. This paper presents the design and simulation of a DC-DC boost converter stepping up the voltage from 12V to 16.8V for a 4.5Ah battery pack. Boost converter parameters, including inductor, capacitor, and switching device, are designed for continuous conduction mode operation at a specified switching frequency. A proportional-integral (PI) controller employing negative feedback control regulates the constant-current-constant-voltage charging by sensing battery current and computing the duty cycle. Simulation is carried out using MATLAB Simulink to observe the ripple voltage spikes across the output voltage by changing the switching frequency. Results show us that 35 KHz provided the least ripple voltage compared to other frequencies on which the system was tested.</em></p> Prathamesh Padamwar, Ashok Suryawanshi, Ganesh Rahate, Arnav Bhawat Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3803 Wed, 01 Jul 2026 00:00:00 +0000 DigiCal: Design and Implementation of a Smart Business Calculator for Offline Financial Inclusion of MSMEs https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3810 <p><em>Modern smartphone-based Point-of-Sale (POS) systems and digital accounting applications have significantly improved financial transaction management in urban commercial sectors. However, many rural and small-scale MSMEs continue to face challenges due to expensive hardware, unstable internet connectivity, limited digital literacy, and a lack of accessible accounting solutions. Traditional calculators remain affordable and easy to use, but they lack transaction logging, GST computation, analytics, customer due management, or secure record storage. To address these limitations, DigiCal was developed as a smart embedded business calculator specifically designed for offline financial inclusion and digital transformation of MSMEs. </em><em>T</em><em>he proposed system combines the familiarity of a conventional calculator with advanced business functionalities, including automated GST calculation, transaction storage, customer due management, expense tracking, sales analytics, and financial reporting. DigiCal follows an offline-first architecture, using a lightweight SQLite database for secure local storage, while also supporting optional cloud synchronization and web-based analytics when network connectivity becomes available. The hardware implementation is based on a Raspberry Pi Zero 2W integrated with a custom 5×7 matrix keypad, TFT display, rechargeable battery system, speaker feedback module, and lightweight Python software architecture. Experimental evaluation demonstrated reliable real-time transaction processing, stable offline operation, accurate GST computation across multiple tax slabs, responsive user interaction, and efficient local data management. The system also exhibited low power consumption and dependable transaction storage under practical operating conditions. By combining affordability, portability, and ease of use, DigiCal provides a practical alternative to expensive POS systems while preserving the simplicity of traditional calculators. The proposed platform can support improved financial record management, operational efficiency, and sustainable business digitization, thereby contributing to greater financial inclusion for MSMEs operating in low-connectivity environments.</em></p> Atharva Gawali, Kalpit Jare, Yash Nayyar, Jyoti Botkar Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3810 Thu, 02 Jul 2026 00:00:00 +0000 Design and Implementation of a Scalable Elevator Control System using RTL-to-GDSII ASIC Flow in Cadence https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3889 <p><em>Elevator control systems are essential real-time embedded applications that ensure efficient and reliable vertical transportation in modern buildings. This paper presents the design and implementation of a Finite State Machine (FSM)-based elevator controller using Verilog Hardware Description Language (HDL), followed by a complete VLSI design flow from Register Transfer Level (RTL) to GDSII generation. The proposed controller efficiently manages floor requests, travel direction, and door operations through a structured FSM architecture with priority-based request scheduling. Functional verification of the RTL design is performed using Cadence Incisive/Xcelium simulation tools to validate system behavior and state transitions. The verified design is synthesized using Cadence Genus, and Logical Equivalence Checking (LEC) is conducted using Cadence Conformal to ensure consistency between RTL and gate-level implementations. Physical design is carried out using Cadence Innovus, including floorplanning, placement, clock tree synthesis, routing, and timing optimization while satisfying design rule constraints. Static timing analysis using Cadence Tempus verifies setup and hold timing requirements for reliable operation. The finalized layout is generated in GDSII format and visualized through the TinyTapeout GDS viewer, demonstrating a complete chip-ready implementation. Experimental results indicate that the proposed design achieves efficient area utilization, optimized timing performance, and low-power operation. The scalable architecture supports both FPGA and ASIC implementations, making it suitable for modern embedded control applications. This work demonstrates a comprehensive industry-standard RTL-to-GDSII design methodology, effectively bridging digital system design and physical chip realization.</em></p> <p><em> </em></p> M.Thamarai, Monika M., Soorya Vela P., Subiksha L., Swetha R. Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3889 Tue, 21 Jul 2026 00:00:00 +0000 Design and Implementation of DMA Controller using Verilog https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3928 <p><em>This article presents the design and implementation of a Direct Memory Access (DMA) controller for a high-performance Global Positioning System (GPS) receiver operating on the Real-Time Executive for Multiprocessor Systems (RTEMS) platform. As GPS receivers process large volumes of navigation and signal data, efficient data transfer mechanisms are essential to achieve high-speed performance and reduce processor workload. To address these requirements, a DMA-based architecture is proposed and integrated into the navigation baseband system. The primary objective of the proposed design is to optimize communication between memory and peripheral components without excessive intervention from the CPU. By allowing data transfers to occur independently, the DMA controller significantly reduces CPU overhead and enables the processor to focus on critical navigation and signal-processing tasks. This approach improves overall system efficiency and responsiveness. The hardware architecture of the DMA Intellectual Property (IP) core is carefully designed to maximize resource utilization and system performance. The design incorporates a multiplexing strategy, enabling multiple data transfer operations to share hardware resources efficiently. This not only reduces hardware complexity but also enhances the flexibility of the system. To ensure reliable and controlled data movement, the architecture employs registers and First-In-First-Out (FIFO) buffers. These components facilitate effective read and write operations while maintaining data integrity and synchronization between system modules. The DMA controller is developed using Verilog Hardware Description Language (HDL), which provides a flexible and scalable framework for hardware implementation. Verilog-based modeling allows the controller to be synthesized and tested across different hardware platforms while maintaining design portability. The controller’s functional behavior, timing characteristics, and data transfer capabilities are thoroughly evaluated during the development process. The proposed DMA controller provides a practical and efficient solution for enhancing the performance of RTEMS-based GPS navigation systems. The integration of optimized hardware architecture, multiplexing techniques, and FIFO-based data management contributes to faster processing and improved system reliability, making the design suitable for high-performance embedded navigation applications.</em></p> Bhavana B. V., Pradeepkumar Naragund, Madhumathy P. Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3928 Fri, 31 Jul 2026 00:00:00 +0000 An Overview of Automated Solutions for Climate-Smart and Sustainable Farming https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3941 <p><em>As the global population surges toward an estimated 10 billion by 2050, traditional agricultural methods are being pushed to their breaking point. To bridge the widening gap between food demand and supply, the integration of technology into farming practices - commonly known as Precision Agriculture has become an absolute necessity. This study presents the design and implementation of an intelligent, microcontroller-based automation system tailored for modern agricultural needs. By leveraging a network of soil moisture, temperature, and humidity sensors, the system continuously monitors the microclimate of the field. The central microcontroller unit acts as the “brain,” processing real-time environmental data to make autonomous decisions regarding irrigation and climate regulation. When soil moisture levels dip below a critical threshold, the system triggers automated water pumps, while abnormal thermal fluctuations activate cooling or ventilation mechanisms. The inclusion of a GSM/Wi-Fi module ensures that farmers remain connected to their crops regardless of geographical distance, receiving instant status updates and emergency alerts. This system not only eliminates the inherent inefficiencies of manual labour but also optimizes resource consumption, marking a paradigm shift toward sustainable, data-driven, and high-yield farming.</em></p> Kazi Kutubuddin Sayyad Liyakat Copyright (c) 2026 Journal of Digital Circuitry Innovations in Electrical Devices https://www.matjournals.net/engineering/index.php/JDCIED/article/view/3941 Mon, 03 Aug 2026 00:00:00 +0000